Highly resistive loads are required in various applications for VLSI digital and analogue integrated circuits. For example, gigaohm resistors may be used as pull-up resistors in memory devices to limit power consumption.
In a known method of providing a linear resistor for a MOS, Bipolar, or Bipolar CMOS (BiCMOS) silicon integrated circuit, a layer of polysilicon is deposited over a thick layer of dielectric, for example, a field oxide provided on a semiconductor silicon substrate. The polysilicon layer is patterned to define a resistor structure and then selectively doped by ion implantation. Typically, the polysilicon resistor structure comprises heavily doped end regions forming ohmic contact electrodes, and a resistive region extending between the contact regions in which the dopant concentration is sufficient to provide a desired resistance value. Low and medium valued resistors for applications in MOS and bipolar digital and analogue integrated circuits (ICs), are typically formed by adjusting the resistivity by selectively doping the layer of polysilicon, e.g. by ion implantation, to obtain n- or p -type ohmic resistors. Advantageously a polysilicon resistor structure can be completely isolated by a layer of dielectric, e.g. silicon dioxide, to reduce potential shunting of the resistor by parasitic current leakage paths. Resistors as described above having low to medium resistance value ranges (i.e. 10-1000 ohm/sq) are linear over a wide voltage range.
Polysilicon resistors may be implemented in any of the four or five layers of polysilicon commonly used in CMOS or BiCMOS processes. For example, as described in U.S. Pat. No. 5,013,678 to Winnerl et. al. entitled "Method of making an integrated circuit comprising load resistors arranged on the field oxide zones which separate the active transistor zones", resistors are formed in a polysilicon layer which forms gate structures of MOS transistors. In another example, described in European Patent Application 0316104A to Hunt et. al. entitled Improvements in Integrated Circuits , a common polysilicon layer is used to provide polysilicon resistors and polysilicon emitters of bipolar transistors.
Amorphous silicon may be used as an alternative to polysilicon, for example as described in a U.S. Pat. No. 047,826 to Keller et. al. entitled "Gigaohm load resistor for BICMOS process" a gigaohm resistor is fabricated from a layer of 1500.ANG. to 2500.ANG. of CVD or sputtered amorphous silicon, heaving heavily doped O+ or N+ head regions which are silicided to form contacts. The resistivity of the amorphous silicon layer is adjusted by ion implantation and is independent of the polysilicon layers forming the gate of CMOS transistors, emitters of bipolar transistors or first capacitor plates. In the latter example, the amorphous silicon layer also formed a second plate of a capacitor or a fuse.
Although highly value resistive loads in the 100k.OMEGA. range may be fabricated reproducibly using conventional CMOS and bipolar CMOS processes, a number of problems arise in using known processes for fabricating gigaohm resistive loads using undoped or very lightly doped polysilicon. The latter is susceptible to process induced damage and defects, which degrade quality, create leakage paths and lead to poor reliability. Non-linearity of conventional known high value polysilicon resistors has restricted use of gigaohm resistors to the leakage current type circuit applications, for example, in high density static random access memories (SRAMS).
In fabricating high value resistances from polysilicon with sheet resistance in excess of megaohm/sq charges are found to be associated with isolating dielectrics, typically deposited oxides, and traps may be generated due to etch damage or exposure of the dielectric to plasma radiation. These charges and traps tend to cause surface conduction modulation in the underlying polysilicon layer and create leakage paths, resulting in resistance degradation. Thus polysilicon and amorphous silicon gigaohm resistors formed as described above, are susceptible to processing or radiation induced surface charges and defects, which may result in highly non-linear current voltage characteristics and significant die-to-die and wafer-to-wafer sheet resistance variability. Resistor performance may be unsatisfactory for analogue circuit designs where gigaohm resistors are required having high linearity and symmetric current-voltage (I-V) characteristics.